基于异构FPGA的卷积网络加速器

doi:10.16451/j.cnki.issn1003-6059.201910007

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Abstract Computational complexity of neural network methods is high, and its application in embedded scenarios is limited. To solve this problem, a convolutional network accelerator based on heterogeneous field programmable gate array is proposed. The sliding window is employed to accelerate the convolution calculation process, and thus the convolution process of different input and output channels can be handled. A 8 bit fixed-point accelerator is designed combining network quantization process, and the usage of computing resources is reduced. Experiments demonstrate that the proposed fixed-point accelerator achieves a higher computing speed and a lower power consumption with a less performance loss.

Key words： Convolutional Neural Network Field Programmable Gate Array(FPGA) Accelerator Parallelism Fixed-Point

Received: 04 June 2019

ZTFLH:

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Fund:Supported by National Natural Science Foundation of China(No.61806081)

Corresponding Authors: ZHONG Sheng, Ph.D., professor. His research interests include pattern recognition, image processing and real-time embedded system.

About author:: ZHOU Xixiong, master student. His research interests include deep neural network and parallel computing;ZHANG Weijun, Ph.D. candidate. His research interests include computer vision and pattern recognition;WANG Jianhui, Ph.D. candidate. His research interests include computer vision, machine learning, deep neural network and pa-rallel computing.

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Cite this article:

ZHOU Xixiong,ZHONG Sheng,ZHANG Weijun等. Heterogeneous FPGA Based Convolutional Network Accelerator[J]. , 2019, 32(10): 927-935.

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http://manu46.magtech.com.cn/Jweb_prai/EN/10.16451/j.cnki.issn1003-6059.201910007 OR http://manu46.magtech.com.cn/Jweb_prai/EN/Y2019/V32/I10/927

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